ABHISHEK BHATTACHARJEE

Associate Professor

Department of Computer Science

Rutgers, The State University of NJ




I direct the Rutgers Systems Architecture Lab. We build hardware architectures and operating systems for next-generation computers. These include classical systems that can process large amounts of data, like data centers, and more exotic computers, like brain-machine interfaces.

You may be familiar with our proposals on coalesced TLBs, which are now implemented in AMD's chips; our research on superpages, which has been integrated in the Linux kernel; and our work on co-developing Psyneulink, a framework for modeling brain function and its relationship to AI.

I am a recipient of the Chancellor's Award for Faculty Excellence in Research at Rutgers and the CV Starr Fellowship at Princeton Neuroscience. I obtained my PhD from Princeton, where I was awarded the Gordon Wu Prize, and BEng from McGill, where I received the British Association Medal for Great Distinction.

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recent teaching and research

    Teaching Materials
  • Advanced Concepts on Address Translation
    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson
  • Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on basic and advanced virtual memory concepts

  • Research Publications
  • Scalable Distributed Shared Last-Level TLBs Using Low-Latency Interconnects, MICRO '18
  • Generic System Calls for GPUs, ISCA '18
    Hosted under the Radeon Open Compute project for ultrascale computing
  • SEESAW: Using Superpages to Improve VIPT Caches, ISCA '18
  • Scheduling Page Table Walks for Irregular GPU Applications, ISCA '18
  • LATR: Lazy Translation Coherence, ASPLOS '18
  • Using Branch Predictors to Predict Brain Activity in Brain-Machine Implants, MICRO '17
    Honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
  • Hardware Translation Coherence for Virtualized Systems, ISCA '17
  • Translation-Triggered Prefetching, ASPLOS '17
    Best paper award nominee
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
  • Efficient Address Translation for Architectures with Multiple Page Sizes, ASPLOS '17
  • COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
  • Architectural Support for Address Translation on GPUs, ASPLOS '14
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal