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Computer Science Department Colloquium

Efficient Stacked DRAM Cache Designs for Multi-Core and Heterogeneous Architectures


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Tuesday, October 30, 2018, 10:30am



In this talk we will describe our group's work on efficient stacked DRAM cache designs. In the first part, we will look at multi-core CPUs workloads and improve the DRAM cache design from the perspective of performance and energy. For improving the performance we proposed an Bi-Modal DRAM Cache, which supports two different cache block sizes and organizes data with high spatial locality as large blocks and the rest as small blocks to improve both hit rate, off-chip bandwidth, and cache capacity utilization. The design also includes a novel Way-Locator, to improve the hit-latency of tags-in-DRAM organization. To improve the energy efficiency of stacked DRAM cache, we proposed Micro-Refresh DRAM Cache design which eliminates more than 90% of refresh overheads in stacked DRAM caches. Interestingly, eliminating refresh of useful cache lines with long reuse distance can potentially improve the overall average memory latency, leading to marginal gains in performance. Incidentally both Bi-Modal cache and MicroRefresh DRAM came were based on insights derived from an analytical performance model for DRAM Cache which we will not describe in the talk.

For Integrated Heterogeneous System Architectures which pack pack latency-oriented CPU cores with throughput-oriented GPU cores, we propose HAShCache, Heterogeneity-Aware Shared DRAM Cache. HAShCache address the disparate demands from CPU and GPU cores for DRAM Cache and memory accesses by prioritizing CPU requests at the DRAM Cache Controller, by selectively bypassing DRAM Cache for CPU requests, and by controlling the occupancy of GPU lines in the DRAM cache.

Speaker: Govindarajan Ramaswamy


Govindarajan Ramaswamy received his B.Sc. degree in Mathematics from Madras University in 1981 and B.E. (Electronics and Communication) and Ph.D. (Computer Science) degrees from the Indian Institute of Science, Bangalore in 1984 and 1989 respectively. He has held postdoctoral research positions and visiting faculty positions at Universities in USA and Canada. Since 1995, he has been with the Supercomputer Education and Research Centre and the Department of Computer Science and Automation, Indian Institute of Science, Bangalore. His research interests are in the areas of High Performance Computing, Compilation Techniques, and Computer Architecture. He has published more than 135 research papers in these areas in international journals and refereed conference proceedings. He is an Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO), ACM Transaction on Parallel Computing (ToPC), and Journal of Parallel and Distributed Computing (JPDC).

Location : CoRE A 301


Santosh Nagarakatte

Event Type: Computer Science Department Colloquium



Indian Institute of Science