Abhishek Bhattacharjee
Assistant Professor, Department of Computer Science, Rutgers University
Affiliated Faculty, Department of Electrical and Computer Engineering, Rutgers University
Ph.D., September 2010, Department of Electrical Engineering, Princeton University

Email: abhib (at) cs (dot) rutgers (dot) edu
Office: CoRE 306, 110 Frelinghuysen Road, Piscataway, NJ
Phone: (732) 445-2001 (x2409)

I am an assistant professor of Computer Science at Rutgers University. I received my Ph.D. (2010) the Department of Electrical Engineering in Princeton University. Prior to that, I completed my Honours B.Eng (2005) from the Department of Electrical and Computer Engineering in McGill University.

Google Scholar
Curriculum Vitae (as of May 2013)
Research
My reseach is nominally in the area of computer architecture but I'm broadly interested in computer systems. My current work deals with the interaction between hardware and the operating system and compilers. Specifically, I am working on architectural support for virtual memory and main memory design for future systems integrating hundreds of cores and hardware accelerators (e.g., GPUs).

Projects and Publications
Architectural support for virtual memory in heterogeneous manycore systems.
Virtual memory is ubiquitous across computing systems today because of its programmability, protection, and modularity benefits. For a great primer on the benefits of virtual memory, check out Peter Denning's summary here. Unfortunately, increased memory capacities, core counts, and heterogeneity are placing great stress on hardware for virtual memory.
  • TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs (TACO 10(1), April 2013, Article 5)
  • CoLT: Coalesced Large-Reach TLBs (MICRO 2012)
  • Shared Last-Level TLBs for Chip Multiprocessors (HPCA 2011)
  • Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors (ASPLOS 2010)
  • Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors (PACT 2009, nominated for the Best Paper Award)

    • Main memory design for manycore systems.
    Main memory has become a serious performance and power bottleneck in computing systems today. We are working on a variety of techniques to design high-performance end energy-efficient memory controllers, devices, and schedulers.
  • CoScale: Coordinating CPU and Memory System DVFS in Server Systems (MICRO 2012)
  • MultiScale: Memory System DVFS with Multiple Memory Controllers (ISLPED 2012)

    • Parallelization and thread criticality.
    As systems embrace tens to hundreds of cores on a chip, intelligent parallelization techniques become crucial for managing performance, power, and other shared resources. Our work invents low-overhead mechanisms to automatically detect bottlenecks in parallel programs and accelerate them for performance/energy.
  • Parallelization Libraries: Characterizing and Reducing Overheads (TACO 8(1), April 2011, Article 5)
  • Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors (ISCA 2009)

    • Performance variability.
    Performance predictability and variability are becoming increasingly important design metrics, especially as systems scale and high utilization/consolidation becomes desirable. This work addresses a range of issues pertaining to performance predictability.
  • Quantifying and Improving I/O Predictability in Virtualized Systems (IWQoS 2013 and longer technical report, DCS-TR-697)

    • Performance modeling.
    As computing systems have become increasingly sophisticated, software simulators struggle to model systems with high fidelity, and reasonable simulation times. We investigate FPGA-based acceleration alternatives to traditinal software simulation.
  • Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation (ISLPED 2008)

    • Teaching Activities
  • CS 507. Advanced Computer Architecture: Spring 2013.
  • CS 505. Computer Structures: Fall 2010, Spring 2012, Fall 2012.
  • CS 211: Computer Architecture: Spring 2011, Fall 2011.

    • Professional Activities
  • Program committees
    HPCA 2012, ISPASS 2012, HiPEAC 2013, WIVOSCA 2013 (co-located with ISCA), HiPEAC 2014.
  • Organizing committees
    ISCA 2013 (industry liaison).

    • Assorted Items
  • Check out the Rutgers Architecture and Programming Language seminars, which I'm co-organizing with Santosh Nagarakatte.
  • Our new systems reading group, attended by intrepid graduate students and faculty.

    • Current Students
  • Binh Pham, PhD.
  • Zi Yan, PhD.
  • Bharath Pichai, MS.

    • Former Students
  • Viswanathan Vaidyanathan, MS 2012.
    Thesis Title: Characterization of TLB and Page Allocation Behavior on Modern Processors.
    First employment: Riverbed Technology.
  • Shankar Ram Balasubramaniam, MS 2012.
    First employment: Riverbed Technology.

    • Collaborators
    I'm lucky to have worked (and still be working!) with the following outstanding colleagues. I try my best to lower their research productivity.
  • Margaret Martonosi, Ricardo Bianchini, Thu Nguyen, Sibren Isaacman, Swastik Kopparty, Tom Wenisch, Dan Lustig, Qingyuan Deng, Cheng Li, Guilherme Cox, Aamer Jaleel, Lisa Hsu, David Meisner.

    • Random Stuff
  • Refreshments at the Drones Club?
  • Cookies. Thanks P. Rex!
  • My childhood hero and scientist extraordinaire.
  • Gear...helps me distinguish between this and this.
  • Barefootball.
  • My homage to Guga and his grunt.
  • Pup John Paw.
  • That thinking feeling.