March 4, Core 11 AM. 

Title: Complexity Effective Transient Fault Detection in Microprocessors
Speaker: A. Sivasubramaniam, Penn St.
Host: Thu Nguyen.

Abstract:

Denser transistor integration and lower voltages are accentuating the
need to provision transient fault handling solutions in future 
microprocessors. Different - informational, spatial, temporal - redundancy
techniques can be employed at the micro-architectural level to address
this problem, with each of them having their pros and cons. Spatial and
informational redundancy solutions can unduly increase the required 
real-estate,
while temporal redundancy techniques such as redundant threading can 
slow down the execution. In this talk, I will present complexity-effective
solutions at the micro-architectural level for transient fault detection 
in processors, to bridge the performance gap between redundant and 
non-redundant
executions.

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Bio:
Anand Sivasubramaniam received his B.Tech in Computer Science from the
Indian Institute of Technology, Madras, in 1989, and the M.S and Ph.D.
degrees in Computer Science from the Georgia Institute of Technology
in 1991 and 1995 respectively. He has been on the faculty at The
Pennsylvania State University since Fall 1995 where he is currently
a Professor. Anand's research interests are in computer systems topics
including architecture, operating systems, parallel and distributed
computing, and performance evaluation. Anand's research has been funded 
by NSF through several grants, including the CAREER award, and from 
industries including IBM, Microsoft and Unisys Corp. He has several 
publications in leading journals and conferences, and is a recipient of the
2002 and 2004 IBM Faculty Awards. He has served on several conference
program committees, on the editorial board of IEEE Transactions on 
Computers,
and is currently an Associate Editor of IEEE Transactions on
Parallel and Distributed Systems. He is a member of the IEEE, IEEE 
Computer Society, and ACM.

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